1. Field of the Invention
The present invention relates to a method of producing a semiconductor device comprising a BiCMOS transistor, more particularly a method of producing a semiconductor device wherein the resistivity of a base polysilicon electrode of a bipolar transistor and the resistivity of source/drain regions of a MOS transistor with an LDD structure are decreased and the production steps can be simplified.
2. Description of the Related Art
In recent years, electronic apparatuses have been made more compact, light in weight, and reduced in power consumption. Along with this, the need for higher integration and miniaturization of semiconductor devices has risen. Thus there has been active effort made to develop a bipolar-CMOS (Bi-CMOS) combining a CMOS having the characteristics of a low power consumption and high integration and a bipolar transistor having the characteristics of high driving force and high speed.
A cross-sectional view of a BiCMOS transistor produced by the method of production of the prior art is shown in FIG. 8. The bipolar transistor part has a double-polysilicon structure suitable for high speeds, while the MOS transistor part is made an LDD structure and the surface of gate electrode and source/drain regions are silicided to achieve miniaturization and higher speed.
In the semiconductor device shown in FIG. 8, a resistor formed by n.sup.- polysilicon 19(n.sup.-) is formed in the polysilicon resistor part. In the vertical NPN transistor part, below the n-type epitaxial layer 6 forming an n-type collector region, an n-type buried collector layer 4 is formed for raising the withstand voltage between base and collector. A p-type base region consisting of an intrinsic base region 36 and a graft base region 38 connected to each other, is formed at the surface of the n-type epitaxial layer 6. An n-emitter diffusion layer 39' is formed at that surface layer.
In the NMOS transistor part, n-type source/drain regions 29 are formed at the surface of a p-well 15. Between the source and drain is formed a gate electrode formed by n.sup.+ polysilicon 19(n.sup.+) via a gate oxide film 18. The surface of the n-type source/drain region 29 and the n.sup.+ gate electrode 19(n.sup.+) are silicided for decreasing the resistance and become titanium silicide 32.
In the PMOS transistor part, an n-type isolation layer 5 is formed for isolation from the p-type substrate 1 and, further, an n-well 17 is formed in the n-type epitaxial layer 6. P-type source/drain regions 30 are formed at the surface layer of the n-well 17, and a gate electrode formed by an n.sup.+ polysilicon 19(n.sup.+) is formed via a gate oxide film 18 between the source and drain. The surface of the p-type source/drain region 30 and the n.sup.+ gate electrode 19(n.sup.+) are also silicided for decreasing the resistance and become titanium silicide 32.
At the surface of the substrate between transistors, a LOCOS 10 is formed. Under the LOCOS 10, a p-type buried isolation region 14 connecting to the p-type Si substrate 1 is formed.
Below, an explanation will be made of a conventional method of producing the above semiconductor device formed with the BiCMOS transistor with reference to FIG. 9A to FIG. 17C. First, as shown in FIG. 9A, a p-type (100) Si substrate 1 is formed with an oxide film 2 by for example thermal oxidation to a thickness of about 10 nm, then a photoresist 3 is deposited over the entire surface. For forming the n-type buried collector layer 4 in the NPN transistor forming region and for forming the n-type isolation layer 5 in the PMOS transistor forming region, openings are formed in the photoresist 3 as shown in FIG. 9A. Using the photoresist 3 as a mask, As, for example, is ion-implanted to form n-buried layers (n-buried collector layer 4 and n-isolation layer 5).
The oxide film 2 is removed, then, as shown in FIG. 9B, an n-type epitaxial layer 6 of a resistance of 1 to 5 .OMEGA.cm is formed to a thickness of about 0.7 to 2.0 .mu.m. At the surface of the n-type epitaxial layer 6, an oxide film 7 is formed by thermal oxidation to a thickness of about 50 nm, then a silicon nitride film 8 is formed by the CVD (chemical vapor deposition) method to a thickness of about 100 nm.
Next, a photoresist 9 is deposited over the entire surface, then, as shown in FIG. 9C, the photoresist 9 is patterned to make openings in the isolation regions. Using the photoresist 9 as a mask, the silicon nitride film 8 and the oxide film 7 are removed, then the Si substrate (n-type epitaxial layer 6) is etched to about 300 to 750 nm. After this, steam-oxidation is performed at 1000.degree. C. to 1050.degree. C. for 3 to 8 hours, whereby, as shown in FIG. 10A, a field oxide film (LOCOS) 10 is formed to a thickness of 600 to 1500 nm.
Next, as shown in FIG. 10B, the silicon nitride film 8 is removed by etching with hot phosphoric acid. Further, as shown in FIG. 10C, the surface of the LOCOS 10 is flattened by light-etching using hydrofluoric acid, for example. Due to this, the oxide film 7 is removed.
As shown in FIG. 11A, a photoresist 11 is deposited over the entire surface, then an opening is formed in the photoresist 11 for forming a collector plug (n.sup.+ sinker) of the NPN transistor. Using the photoresist 11 as a mask, phosphor (P) is ion-implanted under conditions of 70 keV in acceleration energy and 5.times.10.sup.15 atoms/cm.sup.2 in dosage, for example. After this, annealing is performed at 1000.degree. C. for 30 minutes to diffuse the impurity, and as shown in FIG. 11B, an n.sup.+ sinker 12 is formed in the NPN transistor.
Further, a photoresist 13 is deposited over the entire surface and, as shown in FIG. 11B, openings are formed in the photoresist 13 for forming a p-type buried isolation region 14 and a p-well 15 of the NMOS transistor. Using the photoresist 13 as a mask, boron B is ion-implanted under conditions of 200 to 720 keV in acceleration energy and 1.times.10.sup.13 to 1.times.10.sup.14 atoms/cm.sup.2 in dosage, for example.
Next, as shown in FIG. 12A, a photoresist 16 is deposited and patterned as required, then an n-well 17 is formed in the PMOS transistor part using the photoresist 16 as a mask. After this, the photoresist 16 is removed. Due to this, the structure shown in FIG. 12B is obtained.
As shown in FIG. 12C, a gate oxide film 18 is formed by thermal oxidation at 850 to 950.degree. C. to a thickness of 15 to 50 nm. A polysilicon layer 19 is formed by the CVD process over the entire surface at a thickness of 150 to 300 nm.
Next, a photoresist 20 is deposited over the entire surface, then, as shown in FIG. 13A, an opening is formed in the photoresist 20 at the MOS transistor forming region. Using the photoresist 20 as a mask, an n-type impurity is ion-implanted in a high concentration to change the polysilicon layer 19 of the MOS transistor forming region into an n.sup.+ polysilicon layer.
Alternatively, the above step of forming the n.sup.+ polysilicon layer may be performed by diffusion of phosphorus (P) from a PSG layer 21, as shown in FIG. 13B. In this case, first, the PSG layer 21 is deposited over the entire surface of the polysilicon layer 19, then the PSG layer 21 is removed except from the MOS transistor forming region. An oxide film 22 is deposited on this and heat treatment is performed. Due to this, an n.sup.+ polysilicon layer 19(n.sup.+) is formed.
Next, as shown in FIG. 14A, a photoresist 23 is deposited, and an opening is formed in the photoresist 23 at the polysilicon resistance forming region. Using the photoresist 23 as a mask, an n-type impurity is ion-implanted in a low concentration to change the polysilicon layer 19 on the polysilicon resistor forming region into an n.sup.- polysilicon layer 19(n.sup.-).
The photoresist 23 is removed, then dry-etching is performed by for example a Cl.sub.2 /CH.sub.2 F.sub.2 /SF.sub.6 gas system using a resist pattern (not shown) to form, as shown in FIG. 14B, gate polysilicon 19(n.sup.+) of the MOS transistors and a polysilicon resistor 19(n.sup.-).
After this, as shown in FIG. 14C, an n-type impurity is ion-implanted into the NMOS transistor forming region using the gate polysilicon 19(n.sup.+) as a mask to form an n-type LDD 24 by self-alignment. Further, a p-type impurity Is ion-implanted Into the PMOS transistor forming region using the gate polysilicon 19(n.sup.+) as a mask to form a p-type LDD 25 by self alignment.
Next, as shown in FIG. 15A, an oxide film (SiO.sub.2) 26 is formed over the entire surface at a thickness of about 200 nm. As shown in FIG. 15B, a photoresist 27 is deposited over the entire surface, and an opening is formed in the photoresist 27 at the MOS transistor forming region. Using the photoresist 27 as a mask, RIE is performed on the oxide 26 and the gate oxide 18 to form an LDD spacer (sidewall) 28 of a width of 0.15 .mu.m.
The photoresist 27 is removed, then, as shown in FIG. 15C, an n-type impurity is ion-implanted into the NMOS transistor forming region using the LDD spacer 28 as a mask to therefore form the n.sup.+ source/drain regions 29. Further, a p-type impurity is ion-implanted into the PMOS transistor forming region using the LDD spacer 28 as a mask to thereby form the p.sup.+ source/drain regions 30.
Next, as shown in FIG. 16A, a refractory metal layer such as a Ti layer 31 is formed by sputtering or another process over the entire surface. By annealing at 500 to 700.degree. C. for about 10 to 30 minutes, the surface of the source/drain regions 29, 30 and the polysilicon 19(n.sup.+) on the gate electrode are silicided as shown as titanium silicide (TiSi.sub.x) 32 in FIG. 16B.
After this, the unreacted parts of the Ti layer 31 formed on the insulating film are removed by wet-etching. Due to this, the structure shown in FIG. 16C is obtained.
As shown in FIG. 17A, an oxide film (SiO.sub.2 film) 33 is formed over the entire surface at a thickness of about 100 nm. Dry-etching is performed on the oxide film 33, the oxide film 26, and the gate oxide film 18 on the active region of the NPN transistor to form an opening and to expose the Si substrate.
Next, a polysilicon layer is formed by the CVD process over the entire surface at a thickness of about 150 to 300 nm and BF.sub.2 is ion-implanted to change the layer to p.sup.+ polysilicon. Next, dry-etching is performed using a resist pattern (not shown) to form the base electrode 34 of the NPN transistor, as shown in FIG. 17B.
As shown in FIG. 17C, an oxide film (SiO.sub.2) 35 is formed by the CVD process over the entire surface at a thickness of about 300 nm. The oxide film 35 and the polysilicon layer (the base electrode 34) on the emitter forming region of the NPN transistor are etched in sequence to form an opening and expose the Si substrate. In the opening of the emitter forming region, BF.sub.2, for example, is ion-implanted under conditions of 30 to 50 keV in acceleration energy and 1.times.10.sup.13 to 1.times.10.sup.14 atoms/cm.sup.2 in dosage to form an intrinsic base region 36 of the NPN transistor.
Moreover, for forming a sidewall at the emitter forming region, an oxide film (not shown) is formed by the CVD process over the entire surface at a thickness of about 600 nm, then annealing is performed at 850 to 900.degree. C. for 10 minutes and the oxide film (not shown) is etchbacked over the entire surface. Due to this, a sidewall 37 for isolating the emitter/base is formed.
Due to the annealing at this time, the p-type impurity diffuses from the polysilicon base electrode 34 of the NPN transistor into the n-type epitaxial layer 6. Thus, a graft base region 38 is formed and is connected to the activated intrinsic base region 36.
Next, for forming the emitter polysilicon 39 (FIG. 8) of the NPN transistor, a polysilicon layer is deposited by the CVD process over the entire surface at a thickness of about 150 nm, then arsenic (As) is ion-implanted under conditions of 30 to 70 keV in acceleration energy and 1.times.10.sup.15 to 1.times.10.sup.16 atoms/cm.sup.2 in dosage. Next, by annealing at 1000 to 1100.degree. C. for 5 to 30 seconds, the impurity diffuses from the emitter polysilicon 39 to form an emitter diffusion layer 39' as shown in FIG. 8. After this, the emitter polysilicon 39 is patterned by dry-etching to leave the emitter part.
Further, as shown in FIG. 8, RIE is performed to form contact holes in the polysilicon base electrode 34 and n.sup.+ sinker 12, that is, collector plug, of the NPN transistor and on the gate polysilicon 19(n.sup.+) and the source/drain regions 29, 30 of the MOS transistors.
Ti/TiON/AlSi are successively sputtered over the entire surface, then etching is performed leaving only the metal layer covering the contact holes to form metal electrodes 40. Due to this, a semiconductor device shown in FIG. 8 is obtained.
However, in the semiconductor device produced by the above method of production in the prior art, since the polysilicon base electrode of the NPN transistor is formed by p.sup.+ polysilicon, there is a problem of an increase in the resistance from the p-type base. When the base resistance is increased, the problems of a decrease in the f.sub.max (maximum oscillating frequency) and an increase in noise arise.
Further, it is necessary to silicide the top of the source/drain regions and the polysilicon gate electrode of the MOS transistor, then form an oxide film over the entire surface (the oxide film 33 formed at a thickness of about 100 nm in the step shown in FIG. 17A). According to the above method of production of the prior art, in the step of patterning the polysilicon base electrode 34 by RIE, the oxide film 33 is required on the PMOS and NMOS parts to prevent the substrate from being etched.
However, due to the formation of the oxide film 33, the step difference becomes larger at the collector plug (n.sup.+ sinker 12) of the NPN transistor and on the source/drain regions 29, 30 of the MOS transistors and the aspect ratio is increased. If the coverage of the metal electrode 40 deteriorates because of the increase in the aspect ratio, the problem also arises that the reliability of the semiconductor device decreases.